Post-silicon validation and debugging is a final process in the development of a semiconductor device in which bugs and other defects are detected in an integrated circuit after manufacture. Accurate post-silicon leakage power modeling requires power measurement across a wide range of temperature conditions. Obtaining power measurements at relatively high temperatures can be expensive and time consuming.
Poor leakage power models may cause margining and loss of opportunity in run-time power management algorithms, e.g., power capping, energy savings, etc. Leakage power is strongly non-linear with temperature, voltage, and process. Therefore, attempting to interpolate leakage power measurements at higher temperatures can lead to inaccurate leakage power models. Errors in models may be worse at slow process corners and higher voltages.
Inaccurate leakage power models can lead to overly optimistic power management policies in which operating frequency of a hardware component, e.g., a processor, is set too high, which can overload and/or overheat the processor and waste energy. On the other hand, inaccurate leakage power models can lead to overly pessimistic power management policies in which operating frequency of the processor is set too low, thereby reducing performance.
Testers can be used to obtain leakage power measurements for individual components in a system. However, testers are relatively expensive. Also, using testers can be time consuming for volume testing.